#FIG 3.1 Landscape Center Metric 1200 2 2 1 0 2 0 13 40 0 36 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5512 6075 7537 2 1 0 2 0 13 40 0 36 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5400 6525 3150 2 1 0 2 0 13 40 0 36 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5400 9112 3825 2 1 0 2 0 13 40 0 36 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5400 9450 4950 2 1 0 2 0 13 40 0 36 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5400 9225 6300 2 1 0 2 0 13 40 0 36 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5400 4725 5287 2 1 0 2 0 13 40 0 36 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5400 4950 6412 2 1 0 2 0 13 40 0 40 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6975 5287 8325 7087 2 1 0 2 0 13 40 0 40 0.0 0 0 12 1 0 2 1 1 1.0 96.0 192.0 6862 5400 4837 4162 1 1 0 2 0 6 15 0 32 0.0 1 0.0 10350 7649 1800 562 8550 7087 12150 8211 1 1 0 2 0 23 15 0 36 0.0 1 0.0 6300 2362 1800 562 4500 1800 8100 2924 1 1 0 2 0 20 15 0 32 0.0 1 0.0 3150 3712 1800 562 1350 3150 4950 4274 1 1 0 2 0 20 15 0 32 0.0 1 0.0 2700 5287 1800 562 900 4725 4500 5849 1 1 0 2 0 20 15 0 32 0.0 1 0.0 3150 6862 1800 562 1350 6300 4950 7424 1 1 0 2 0 13 15 0 32 0.0 1 0.0 5625 8212 1800 562 3825 7650 7425 8774 1 1 0 2 0 6 15 0 32 0.0 1 0.0 11475 4837 1800 562 9675 4275 13275 5399 1 1 0 1 0 11 15 0 32 0.0 1 0.0 6974 5287 1349 421 5625 4866 8323 5708 4 1 0 8 0 16 18.0 0.0 4 352.0 2048.0 10350 7985 Codeerzeugung\001 4 1 0 8 0 16 18.0 0.0 4 352.0 3072.0 10350 7649 Retargierbare Compiler,\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1216.0 6975 5400 Codesign\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1712.0 6300 2250 Spezifikation:\001 4 1 0 8 0 16 18.0 0.0 4 352.0 2864.0 6300 2587 SDL, C/C++, VHDL, ...\001 4 1 0 8 0 16 18.0 0.0 4 352.0 2208.0 3150 3599 Zielarchitekturen,\001 4 1 0 8 0 16 18.0 0.0 4 352.0 2528.0 3150 3937 Architektursynthese\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1184.0 2700 5175 HW/SW-\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1856.0 2700 5511 Partitionierung\001 4 1 0 8 0 16 18.0 0.0 4 352.0 2304.0 3150 6862 HW/SW-Interface\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1840.0 3150 7198 und Protokolle\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1456.0 5625 8325 Prototyping\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1504.0 11475 4725 Verifikation,\001 4 1 0 8 0 16 18.0 0.0 4 352.0 2144.0 11475 5061 Model-Checking\001 6 12600 2700 9000 3824 1 1 0 2 0 6 15 0 32 0.0 1 0.0 10800 3262 1800 562 9000 2700 12600 3824 4 1 0 8 0 16 18.0 0.0 4 352.0 1952.0 10800 3262 Co-Simulation,\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1392.0 10800 3600 Debugging\001 -6 6 13050 5737 9450 6861 1 1 0 2 0 6 15 0 32 0.0 1 0.0 11250 6299 1800 562 9450 5737 13050 6861 4 1 0 8 0 16 18.0 0.0 4 352.0 2208.0 11250 6299 Modellierung und\001 4 1 0 8 0 16 18.0 0.0 4 352.0 1984.0 11250 6635 Absch\344tzungen\001 -6 2 2 0 1 7 0 5 0 -1 0.0 0 0 0 0 0 5 0 0 13500 0 13500 9450 0 9450 0 0 2 1 0 1 0 0 5 0 -1 0.0 0 0 12 0 0 2 450 9000 13050 9000 2 1 0 1 0 0 5 0 -1 0.0 0 0 12 0 0 2 450 1125 13050 1125 4 0 0 0 0 16 11.0 0.0 4 208.0 2176.0 1350 9330 Systemsimulation - 10.02.99\001 4 0 0 0 0 1 35.0 0.0 4 672.0 4432.0 1350 900 Codesign: Themen\001